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Layout
The VDS is located between the target wires (z= -55 mm and 0 mm) and the
spectrometer magnet at z = 2.3 m. It comprises 7 superlayers of detector
planes, which - typical for a forward microvertex spectrometer - are
arranged perpendicularly to the beam axis. Its angular coverage is consistent
with the magnetic spectrometer acceptance, 10 mrad to 160 mrad horizontally,
and 10 mrad to 250 mrad vertically; in the center of mass system that
coverage corresponds to 90% of 4pi.
Side and perspective views
of the geometrical detector arrangement are shown separately.
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Challenges
The requirements on the VDS imply challenges for the design of detectors,
electronic readout, as well as for the mechanical and thermal engineering.
Continuous R&D efforts are devoted to approach the optimum solution with
respect to performance and cost effectiveness. The various topics include:
Detectors
The baseline design assumes AC coupled double-sided silicon detectors of
50x70 mm^2 active area, 280 µm thickness, and strip resp. readout pitches of
typically 25 µm and 50 µm. Single-sided detectors are considered to be a
backup solution if radiation damage issues would justify their use.
The
detectors
have been designed by the
semiconductor laboratory
of the
MPI Munich and they are produced both there as well as by commercial
companies. The special design of those detectors allows operation at
reverse bias voltages exceeding 300 V.
Electronic Readout
The requirements on the VDS detector readout closely ressemble those of the
LHC tracking detectors, and it is no coincidence that the HERA-B VDS is using
the architecture developed by the
RD20 group
that has been also adopted by the CMS detector.
It is based on a relatively slow low noise amplifier of 50 to 75 ns peaking
time. Detector signals are sampled at the bunch crossing frequency of 10.6 MHz
and stored in a 128 cell deep analog pipeline to await the Level-1 trigger
decision. In the event of a Level-1 trigger, the appropriate analog samples
of 2x128 detector channels are multiplexed to one serial output line. Occuring
concurrently with data sampling, readout at up to 40 MHz is practically
dead-timeless. Prototype chips, HELIX and its support chip SUFIX, processing
128 input channels have been implemented at the
Heidelberg ASIC
laboratory
for a standard CMOS process.
The time-multiplexed output signals of the frontend chips are transmitted
via analog optical fiber links to the counting room for digitization in
VDS specific front-end driver modules. The interface to the detector wide
data acquisition system is common to all subdetectors and represented by the
'SHARC boards' each of which is equipped with six ADSP 21060 digital signal
processors including memory for the second level buffers. In case of the
VDS, the task of these digital signal processors will be to do on-line the
pedestal subtraction, common baseline shift correction, cluster finding,
data sparsification formatting for a total of about 150.000 detector channels.
Hardware Setup
The detector system including the target wire assemblies
are contained in a vacuum vessel with an exit window and an integrated tapering
beam pipe for the rest of the HERA-B experiment at the one end and a connection
to the standard beam line system at the other.
The overall length of the vessel is about 2.5 m and its maximum radius is 58 cm.
The exit window is kept as thin as possible, i.e. about 3 mm if fabricated
out of aluminium.
The silicon wafers are maintained at a secondary vacuum of 10^{-6} mbar and
the main stainless steel vessel at 10^{-8} mbar.
Status
The HERA-B experiment has been fully approved by DESY in February 1995, and the
detector is expected to be completed and commissioned in 1998. To gain early
experience, some detector components were already installed during the 1995/96
shutdown period including the spectrometer magnet, parts of the muon system
and prototypes of the electromagnetic calorimeter counters, of the transition
radiation detectors and the tracking chambers
(see A.Spengler, NIM A384 (1996) 106 for more details) .
As to the VDS, the 1995/96 installation included
June 1997, K.T.Knöpfle (ktkno@mpi-hd.mpg.de)